T-engine

Automatic Transistor-Level Schematic Generation

The Nlview® basic engines automatically generate schematics at the gate, register-transfer and block-level. With the T-engine™ option, Concept Engineering provides advanced visualization technology to EDA tool developers who develop tools for the transistor-level (or device-level). When integrated with EDA tools, Concept Engineering's T-engine helps designers of electronic integrated circuits (ICs) and systems on a chip (SoCs) to visualize such critical information as circuit structure, parasitic components, timing data and signal values at the transistor-level, so they can more easily and accurate tune designs for maximum performance. T-engine also makes it easier to understand output results of cell and IP-block characterization tools.

Transistor-Level Algorithms

In response to demand from the electronic design automation (EDA) and the semiconductor industries, Concept Engineering has developed completely new algorithms that generate easy-to-read transistor-level schematics. T-engine recognizes common device-level circuit patterns, and can detect and analyze serial/parallel circuit paths. It also can perform current flow analysis (i.e., power-to-ground flow) and logic flow analysis including both left-to-right flow and reverse-flow detection for feedback. In addition, T-engine uses new place-and-route techniques developed by Concept Engineering. As a result T-engine is able to produce clean transistor-level schematics for complex transistor designs. In addition Concept Engineering's new schematic engine also supports a mix of transistor-level technology with gate-level or block-level technologies in a single schematic diagram.

Widest Platform Availability

T-engine is available for many GUI development platforms including: Qt, PyQt, Java, wxWidgets, Tcl/Tk, Perl/Tk, MFC, JavaScript/WebAssembly (runs inside Web browsers) and as a GUI-less version. For more details, see the main Nlview Widgets page.

At a Glance