Our debugging and visualization software tools help electronic design engineers to easily understand, debug, optimize and document electronic designs (IC, SoC, FPGA). StarVision, RTLvision, GateVision and SpiceVision are customizable and scriptable debugging tools for electronic design engineers.
RTLvision® is a RTL Debugger that reads Verilog, VHDL, and SystemVerilog as well as Liberty. It elaborates the given RTL and displays schematic diagrams, optimized for human readability.
GateVision® is a gate-level Debugger that reads post-synthesized Verilog or EDIF netlists, or LEF/DEF connectivity and displays them as schematic diagrams.
SpiceVision® is a transistor-level Debugger that reads almost any Spice netlist (like HSpice, Eldo, Spectre, CDL or Calibre) and the post-layout parasitic formats DSPF and SPEF.
StarVision® is a Mixed-Signal Debugger that reads RTL, gate-level, SPICE-level and IP descriptions and allows comprehensive debug for complex SoCs and AMS designs.
For a free tool evaluation, please register with the "Register" button to get a login-name and password for the download and a temporary FLEXnet license key from us or our representatives. All Vision tools are available for these Platforms.
Our automatic schematic generation, navigation and viewing technology is available as Nlview software component for EDA tool developers.
T-engine™ is an option to Nlview for creating transistor-level schematic diagrams. It is combinable with all supported GUI platforms. Please check out our online SVG Demo that creates SVG files with T-engine.
S-engine™ is an option to Nlview for creating system-level schematic diagrams. It is combinable with all supported GUI platforms. It includes features that help software developers to build block level schematic editors or SoC/IP assembly tools.