SpiceVision® PRO takes SPICE netlists and SPICE models and generates clean, easy-to-read transistor-level schematics, circuit fragments, and design documentation to speed up circuit design, circuit debugging and circuit optimization at the transistor-level (device-level, SPICE-level). Please check out the Demo Video: SPICE netlist debugging basics.
Spice circuits and Spice models are the common currency of the EDA world. They are generated by many EDA tools and provide a description of the circuit at the lowest level of components: the transistors, capacitors, resistors and even the interconnect, that combine to produce, for example, an IC. But for all but the most trivial design, Spice files are difficult to read and understand. SpiceVision PRO generates circuit schematics on screen, speeds up debugging and helps to solve design problems in: Digital Circuits, Mixed-Signal ASICs, Analog Circuits, Printed Circuit Boards and MEMS.
Customization — a Tcl based application program interface (API) allows access to the internal database and graphical user interface (GUI). Users can analyze the design data and generate user-specific design reports and design checks.
Multi-level — the browser displays multiple hierarchy levels, from top level overview to all sub-circuit levels, while multiple windows display the hierarchy tree, source code and schematic diagrams. The user can select areas of interest from a results list, generated by a powerful search engine, to generate circuit diagrams.
Cone Window — the Cone Window, an "intelligent magnifying glass", displays selected fragments, including critical circuit paths. These circuit fragments can be transferred to a simulator as a separate SPICE file (SPICE netlist export), for partial simulation, often running 10 to 100 times faster than a full circuit simulation.
Simplification and Automatic Logic Recognition — SpiceVision PRO can simplify the schematic, merging components in parallel, such as capacitors, or creating a non-parasitic view, showing only functionality. Automatic logic recognition creates digital logic symbols from pure SPICE-level netlists for easy design exploration.
Post-Layout Debugging — Layout extraction tools generate very large and complex DSPF netlists and SPF netlists with different critical paths. These paths can be extracted, displayed, and saved for fast critical path simulation (parasitic analysis option).
IP — specific parts of a design can be cookie-cut (extracted) from the complete design and saved as a SPICE netlist for use as new IP or for detailed SPICE simulation.
Virtuoso/SKILL — the Virtuoso Schematic Editor environment option, based on the Cadence SKILL language, automatically generates critical paths or sections of a circuit and exports them into the Cadence Virtuoso Schematic Editor environment.
Fast SPICE Viewer — Within seconds SpiceVision PRO gives engineers an
extra level of understanding of the circuits that are defined in their SPICE
netlist files. It is easier to debug and optimize designs and devices can move
into production earlier and with a higher degree of confidence.
|Creates schematics from Spice files||Schematics provide easier and faster debugging for complex circuits. Supported dialects include SPICE, HSPICE, Spectre, Calibre, CDL, DSPF, SPEF, Eldo, PSPICE and IBIS|
|64-bit support (Solaris, AIX, AMD64 Linux, Itanium Linux).||Higher performance and increased capacity, for larger and more complex designs|
|Automatic Logic Recognition||Creates digital logic symbols and schematics from pure SPICE netlists for easy design exploration|
|Powerful GUI||Multiple views, including tree, schematic, cone and source file for increased circuit understanding plus drag and drop between different views|
|Cone Window||Incremental schematic navigation for big designs, SPICE netlist export|
|Non-Parasitic view||Displays CMOS function without parasitic structures for comprehension of circuit|
|Tcl UserWare API||Allows interfacing with tool flow and user customization|
|Fragment save||Fragments of circuits can be saved as Spice files for future reuse as IP, or for partial simulation (SPICE netlist writer)|
|Schematic export option||Export schematics and schematic fragments into Cadence Virtuoso Schematic Editor and EDIF 2.0.0 schematic files for further optimization and debugging|
|Predefined symbols||Symbols for components (resistors, capacitors, transistors, current and voltage sources etc) supplied as standard; can link to external symbol libraries|
|Virtuoso/SKILL Export||To export schematics and schematic fragments to Cadence Virtuoso schematic editor for further optimization and debugging. More info ...|
|EDIF 2.0.0 Schematic Export||To export schematics and schematic fragments into EDIF 2.0.0 schematic files.|
|Parasitic Analysis Package||Allows visualization and analysis of parasitic networks (DSPF, RSPF, SPEF) and provides capabilities to create SPICE netlists for critical path simulation.|