FREIBURG, Germany and Santa Clara, Calif. - June 2, 2004 - Concept Engineering and Hier Design Inc. today announced a worldwide OEM license agreement to bundle Concept Engineering's NlviewJA Widget, a JAVA-based visual debugging software engine, into Hier Design's PlanAhead™ hierarchical floorplanning and analysis software. Concept's Nlview engine is the industry-standard schematic generation, viewing, and debugging software for electronic design automation (EDA) tool developers who develop graphical user interfaces for EDA tools.
With the incorporation of the NlviewJA Widget into PlanAhead, customers designing electronic systems on a chip (SoCs) and high-complexity field programmable gate arrays (FPGAs) gain access to an easy-to-use graphical user interface. It intuitively displays components, connectivity, and critical paths, and lets designers quickly visualize and fix problems in their designs.
"We decided to OEM Concept Engineering's technology into our products because it's the most advanced visualization technology available. We also were able to save development costs, bringing PlanAhead to market much faster than if we had developed our own schematic viewing technology," said Dino Caporossi, vice president of marketing at Hier Design.
"Our ongoing investment in advanced visualization technology has resulted in more and more customers relying on us for their GUI, and we're pleased to have met Hier Design's advanced technical specification for their new PlanAhead product," said Gerhard Angst, CEO of Concept Engineering. "The design of complex FPGAs requires more sophisticated, ASIC-like tools and methodologies. Our partnership with Hier Design makes it easier for the PlanAhead user to plan and analyze multiple physical implementations, maximizing design space exploration by more quickly identifying optimal implementations."
Concept Engineering's visualization engine is connected with PlanAhead's netlist and floorplan views to provide cross highlighting from the analysis report to critical paths graphically traced within the floorplan. Designers can debug logic paths by selectively clicking pins and nets in the schematic cone view and by tracing the corresponding interconnect in the floorplan.
Product demonstrations for the Nlview Widget family and PlanAhead will be given at the Design Automation Conference (DAC) in San Diego, Calif., June 7-12, 2004, in the Concept Engineering and Hier Design booths, respectively.
About Nlview Widgets
The Nlview Widget family provides a broad range of components for GUI development - Qt, Java, Tcl/Tk, MFC, and Perl/TK - for automatic schematic generation, viewing, and debugging at all design levels: transistor, gate, block, register-transfer, and system. Nlview Widgets relieve EDA tool designers of the tedium and productivity loss of having to develop their own schematic generation software by providing a set of robust and flexible software components for automated schematic generation and viewing. By adopting Nlview Widgets, developers can quickly realize GUIs for EDA products with shorter design cycles and lower development and maintenance costs.
About PlanAhead Hierarchical Floorplanner
The PlanAhead hierarchical floorplanning and analysis software accelerates design, providing a fast, less iterative path from logic synthesis to physical design. It increases performance and reduces design iterations by giving advanced insight into the place and route process. It provides a hierarchical, block-based and incremental design methodology, enabling designers to change only one part of the design and leave the rest intact, shortening design iterations and increasing performance predictability. PlanAhead offers seamless integration with the Xilinx design flow by encapsulating place and route commands directly in the graphical user interface, and supports the Xilinx Virtex-II and Spartan3 device families. PlanAhead is supported on Solaris, Linux, and Windows operating systems.
About Concept Engineering
Concept Engineering is a privately held company based in Freiburg, Germany, founded in 1990 to develop and market innovative schematic generation and viewing technology for use with logic synthesis, verification, test automation and physical design tools. The company's customers are primarily original equipment EDA tool manufacturers (OEMs), in-house CAD tool developers and semiconductor companies. For more information see http://www.concept.de
About Hier Design
Founded in 2001, Hier Design Inc. is an electronic design automation (EDA) industry newcomer creating the next EDA beachhead by helping fuel the movement from application specific integrated circuits (ASICs) to high-speed, highly complex field programmable gate arrays (FPGAs). Its investors include ITU Ventures, Xilinx Inc. (NASDAQ: XLNX - News), Cadence Design Systems Inc. (NYSE: CDN - News), Innotech Corporation, Lanza Tech Ventures and private investors. Corporate headquarters is located at: 2350 Mission College Boulevard, Suite 850, Santa Clara, Calif. 95054. Telephone: (408) 982-8240. Facsimile: (408) 982-3838. Email: email@example.com. More details can be found at the Hier Design website located at: http://www.hierdesign.com
Gerhard Angst, +49-761-47094-0,
Cayenne Communication LLC
Michelle Clancy, 252 940-0981, firstname.lastname@example.org
Public Relations for Hier Design Inc.
Nanette Collins, 617 437-1822, email@example.com
Hier Design Inc.
Dino Caporossi, 408 982-8257, firstname.lastname@example.org