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Press Release

Concept Engineering Announces a DSPF Interface for SpiceVision® PRO and SGvision® PRO

New Interface Enables Engineers to Fully Understand the Impact of Parasitic Elements on Their Designs

NICE, France - April 16, 2007 - Concept Engineering today announced a new detailed standard parasitic format (DSPF) interface to the company′s SpiceVision® PRO and SGvision® PRO products that will enable design engineers to better understand, manage, and fix parasitic structures within complex digital, mixed-signal, and analog ICs.

Using nanometer process technologies, integrated circuit (IC) designers are able to build systems comprising millions of transistors. However, extremely compact devices and more complex interconnect structures require detailed modeling of parasitic effects and make it necessary to conduct transistor-level post-layout analysis and simulation in order to detect potential functional failures.

The layout of an integrated circuit (IC) contains an enormous number of parasitic devices resulting from the interconnections and components of the chip. Such parasitic networks, often modeled as DSPF files, describe the parasitic resistance and capacitance of signal nets within an IC.

"The new DSPF capability was developed in response to customer requests to help them better understand and manage parasitic structures on their ICs," said Gerhard Angst, president and CEO of Concept Engineering. "This new capability is based on our existing market-proven SpiceVision® PRO platform, currently in use by more than 70 semiconductor companies and electronics manufacturers world wide."

DSPF is widely supported by many electronic design automation (EDA) tool vendors. With the new DSPF interface, design engineers using SpiceVision PRO and SGvision PRO will be able to easily read, explore, and analyze parasitic structures in order to better understand, and manage parasitic elements within their IC designs. The interface generates and displays schematics of the parasitic networks, providing engineers with very detailed information about the structure and values of interconnections on their chips. Cross probing from parasitic schematics to DSPF source code enables engineers to know the exact location of parasitic devices in the chip layout.

Concept Engineering′s DSPF capability will be demonstrated for the first time at stand # R34 at the 2007 DATE (Design Automation and Test in Europe) Conference in Nice, France from April 17 to 19.

About Concept Engineering

Concept Engineering is a privately held company based in Freiburg, Germany, founded in 1990 to develop and market innovative schematic generation and viewing technology for use with logic synthesis, verification, test automation and physical design tools. The company′s customers are primarily original equipment EDA tool manufacturers (OEMs), in-house CAD tool developers and semiconductor companies. For more information see http://www.concept.de

CONTACTS: Concept Engineering
Gerhard Angst, +49-761-47094-0, [email addr]
Cayenne Communication LLC
Michelle Clancy, +1-252-940-0981, michelle.clancy@cayennecom.com